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HC5503PRC
Data Sheet June 2004 FN4806.3
Low Cost SLIC For Large Telecom Switches
The HC5503PRC is a low cost SLIC optimized for large Telecom switches. It combines a flexible voltage feed architecture with the Intersil latch-free DI bonded wafer process, to provide a low component count, carrier class solution at very low cost. The re-configurable design permits simple, economical solutions for campus-wide call center and PBX applications. External components can be used in conjunction with the high battery voltage capability to meet the complex impedance and long loop drive requirements of Central Office switches, worldwide.
Features
* Wide Operating Battery Range (-40V to -58V) * Single Additional +5V Supply * 30mA Short Loop Current Limit * Ring Relay Driver * Switch Hook and Ring Trip Detect * Low On-Hook Power Consumption * On-Hook Transmission * ITU-T Longitudinal Balance Performance * Loop Power Denial Function
PKG. DWG. # M24.3 M24.3
Ordering Information
TEMP. PART NUMBER RANGE (C) HC5503PRCB HC5503PRCBZ (Note) HC5503PRCBZ96 (Note) HC5503PRCR HC5503PRCRZ (Note) HC5503PRCRZ96 (Note) 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 PACKAGE 24 Ld SOIC 24 Ld SOIC (Pb-free)
* Thermal Protection * Supports Tip, Ring or Balanced Ringing Schemes * Low Profile SO and QFN Surface Mount Packaging * Pb-free Available
24 Ld SOIC Tape & Reel M24.3 (Pb-free) 32 Ld 7x7 QFN 32 Ld 7x7 QFN (Pb-free) 32 Ld 7x7 QFN Tape & Reel (Pb-free) L32.7x7 L32.7x7 L32.7x7
Applications
* Central Office, PBX, Call Centers * Related Literature - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 1999, 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HC5503PRC Block Diagram
RING RELAY DRIVER
RD
4-WIRE INTERFACE VF SIGNAL PATH
TX RX
RFS C2
RING TRIP DETECTOR
TIP TF RING RF THERMAL LIMIT VBAT VCC AGND BGND DGND BIAS + C1 OUT +IN -IN
2-WIRE INTERFACE
LOOP CURRENT DETECTOR LOGIC INTERFACE
SHD RS RC PD
2
HC5503PRC
Absolute Maximum Ratings
Maximum Continuous Supply Voltages (VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V (VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V (VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Information
Thermal Resistance (Typical, Note 2, 3)
JA (C/W)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0C to 70C Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V Positive Supply Voltage (VB+) . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Negative Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . -40V to -58V High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V Subscriber Loop Resistance . . . . . . . . . . . . . . . . . . . 200 - 1800
24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 32 Lead 7x7 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. JA is measured with the component mounted on an evaluation PC board in free air. 3. JA for the QFN package is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features including conductive thermal vias. See Tech Brief TB379 and TB389 for additional information and board layout consideration
Electrical Specifications
PARAMETER On Hook Power Dissipation Off Hook Power Dissipation On Hook IB+ Off Hook IB+ On Hook IBOff Hook IBOff Hook Loop Current Off Hook Loop Current Fault Currents TIP to Ground RING to Ground TIP to RING TIP and RING to Ground Ring Relay Drive VOL Ring Relay Driver Off Leakage DC Ring Trip Threshold Switch Hook Detection Threshold Loop Current During Power Denial Dial Pulse Distortion Receive Input Impedance Transmit Output Impedance
Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50, RS = 100, Typical Parameters. TA = 25C. Min-Max Parameters are Over Operating Temperature Range CONDITIONS ILONG = 0 (Note 4) RL = 600, ILONG = 0 (Notes 3, 4) RL = , ILONG = 0 RL = 600, ILONG = 0 RL = , ILONG = 0 RL = 600, ILONG = 0 RL = 1800 (ILOOP = 0) RL = 200, ILONG = 0 (Note 3) MIN 18 25 TYP 113 750 1.4 2.8 2.2 31 30 MAX 35 UNITS mW mW mA mA mA mA mA mA
IOL = 62mA VRD = 12V, RC = 1 = HIGH, TA = 25C 8.1 5.0 RL = 200 (Note 4) (Note 4) (Note 4) 0 -
27 55 30 69 0.2 10.8 7.5 3.2 110 10
0.5 100 13.5 10 0.5 20
mA mA mA mA V A mA mA mA ms k
3
HC5503PRC
Electrical Specifications
PARAMETER 2-Wire Return Loss SRL LO ERL SRL HI Longitudinal Balance 2-Wire Off Hook (Note 4) 2-Wire On Hook (Note 4) 4-Wire Off Hook Insertion Loss 2-Wire to 4-Wire, 4-Wire to 2-Wire Frequency Response Idle Channel Noise 2-Wire to 4-Wire, 4-Wire to 2-Wire At 1kHz, 0dBm Input Level, Referenced 600, RP = RS = 150 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level, RP = RS = 150 (Note 4) RP = RS = 150 (Note 4) Absolute Delay 2-Wire to 4-Wire, 4-Wire to 2-Wire Trans Hybrid Loss Overload Level 2-Wire to 4-Wire, 4-Wire to 2-Wire Level Linearity 2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4) At 1kHz, (Note 4) Referenced to 0dBm Level, RP = RS = 150 +3 to -40dBm -40 to -50dBm -50 to -55dBm Power Supply Rejection Ratio VB+ to 2-Wire VB+ to Transmit VB- to 2-Wire VB- to Transmit VB+ to 2-Wire VB+ to Transmit VB- to 2-Wire VB- to Transmit Logic Input Current (RS, RC, PD) Logic Inputs Logic `0' VIL Logic `1' VIH Logic Outputs Logic `0' VOL Logic `1' VOH ILOAD 800A, VB+ = 5V ILOAD 40A, VB+ = 5V 2.7 0.1 0.5 5.0 V V 2.0 0.8 5.5 V V 0V VIN 5V 200 - 16kHz, RL = 600, RP = RS = 150 RP = RS = 150 (Note 4) 30 - 60Hz, RL = 600 0.05 0.1 0.3 dB dB dB Balance Network Set Up for 600 Termination at 1kHz, RP = RS = 150 (Note 4) VB+ = +5V, RP = RS = 150 (Note 4) 1.5 VPEAK RP = RS = 150 (Note 4) 30 40 2 s dB 1 -89 5 -85 dBrnC dBm0p 1VRMS 200Hz - 3400Hz, (Note 4) IEEE Method 0C TA 75C, RP = RS = 150 Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50, RS = 100, Typical Parameters. TA = 25C. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS (Referenced to 600 + 2.16F), RP = RS = 150 (Note 4) MIN TYP MAX UNITS
-
15.5 24 31
-
dB dB dB
53 53 50
58 58 58 0.05 0.02
0.2 0.05
dB dB dB
-
dB dB
15 15 15 15 30 30 30 30 -
-
100
dB dB dB dB dB dB dB dB A
4
HC5503PRC
Electrical Specifications
PARAMETER UNCOMMITTED OP AMP SPECIFICATIONS Input Offset Voltage Input Offset Current Input Bias Current Differential Input Resistance Output Voltage Swing Output Resistance Small Signal GBW NOTES: 4. ILONG = Longitudinal Current. 5. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. (Note 4) RL = 10K, VB+ = 5V AVCL = 1 (Note 4) (Note 4) 5 10 20 1 3 10 1 mV nA nA M VPEAK MHz Unless Otherwise Specified, VB- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP = 50, RS = 100, Typical Parameters. TA = 25C. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS MIN TYP MAX UNITS
Pin Descriptions
24 PIN DIP/SOIC 1 7x7 QFN 28 SYMBOL TIP DESCRIPTION An analog input connected to the TIP (more positive) side of the subscriber loop through a sense resistor (RS) and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. An analog input connected to the RING (more negative) side of the subscriber loop through a sense resistor (RS) and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into the line at this node and RF is isolated from RFS via a relay. Positive Voltage Source - Most positive supply. VB+ is typically. Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VB-. Typical value is 0.3F, 30V. Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC microcircuit. Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to 5V. Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. Tip Feed - A low impedance analog output connected to the TIP terminal through a sense resistor (RS). Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. Ring Feed - A low impedance analog output connected to the RING terminal through a sense resistor (RS). Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to -58V. Frequently referred to as "battery". Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents exceeding the switch hook threshold. Used during production test. Leave disconnected.
2
31
RING
3 4 5 6 7
32 1 3 4 5
RFS VB+ C1 DG RS
8 9
6 7, 8
RD TF
10
9, 10
RF
11 12 13 14
11 12 13 14,19
VBBG SHD NC
5
HC5503PRC Pin Descriptions
24 PIN DIP/SOIC 15 7x7 QFN 15 (Continued) SYMBOL PD DESCRIPTION Power Denial - A low active TTL - Compatible logic input. When enabled, the ring feed voltage collapses to the tip feed voltage (~4V). The DC feed is disabled, but the AC transmission is maintained. The switch hook detect (SHD) is not necessarily valid, and the relay driver (RD) output is disabled. Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). Leave disconnected. The analog output of the spare operational amplifier. The inverting analog input of the spare operational amplifier. The non-inverting analog input of the spare operational amplifier. Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals. Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This capacitor is required for the proper operation of ring trip detection. Recommended value 0.82F 10% 10V non-polarized. Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. Transmit Output, Four Wire Side - A low impedance analog output proportional to the loop current. Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. No internal connection.
16
16
RC
17 18 19 20 21 20 21 22 23
NC OUT -IN +IN RX
22
25
C2
23 24
26 27
AG TX
2, 17, 18,24, 29, 30,
NC
NOTE: All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
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HC5503PRC Functional Diagram
RS RC RD 1/2 RING RELAY RP TIP DIFF AMP + TF VBSECONDARY PROTECTION BG VBRFS 1/2 RING RELAY RING RP RING VOLTAGE VBRS: 100; 1/2W to 2W depending on surge requirements RP: 50; 1/2W to 2W depending on surge requirements RING PD SLIC MICROCIRCUIT -1 RS RX RECEIVE INPUT RF LOOP CURRENT LIMITER LINE DRIVERS BATTERY FEED +1 +IN + OP AMP -IN OUT TX TRANSMIT OUTPUT RING CONTROL RING TRIP LOOP MONITORING SHD SWITCH HOOK DETECTION
RING SYNC RING COMMAND
TIP
RS 2-WIRE LOOP
POWER DENIAL
7
HC5503PRC
SLIC FUNCTIONAL SCHEMATIC SOIC PIN NUMBERS SHOWN
21 RX 22 C2 11 VBAT 12 BAT GND 23 ANA GND VB+ VB1 VB2 VB3 VB4 VB5 5V 6 DIG GND 4 VB+ 20 + 19 VB+ 18 OUT
VOLTAGE AND CURRENT BIAS NETWORK R17 VB2 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11 RING TRIP DETECTOR R12 R7 TIP 1 RING FEED SENSE 3 R8 R10 R9 R22 R3 RING 2 R4 R1 R2 R16 R15 R11 VBAT V + VBAT R23 B + + R5 VB+ QD3 QD36 V B+ A-200 LONG'L I/V AMP IB7 VBAT IB8 R20 + VBAT VB4 5V
A-500 OP AMP VBAT
V B+ TF 9 VBAT A-400 TIP FEED AMP IB4
+
IB3
-
5V IB10 VB+
-
GK NC 14
GND SHORTS CURRENT LIMITING IB1
VB+ A-100 TRANSV'L I/V AMP SWITCH HOOK DETECTOR VB+
+ VB3 VBAT STTL AND LOGIC INTERFACE
NC 17
IB6
VBAT R6
SH + IB6 QD27 QD28 THERMAL LIMITING RFC
SHD 13
VB1
VBAT/2 REFERENCE VB2 R14
RC 16
R18
RF 10 VBAT IB5 A-300 RING FEED AMP +
R21
LOAD CURRENT LIMITING IB2
R19
VB5
VB5
PD 15
+
VBAT
R13 VBAT VBAT
C1 5
TX 24
RS 7
RD 8
8
HC5503PRC
LOGIC GATE SCHEMATIC
GK
1
2
LOGIC BIAS DELAY 6 4 8 3
5 7 9 12
SH
16 10
13 11 15 TTL TO STTL TTL TO STTL TTL TO STTL TO R21 C SCHOTTKY LOGIC 14 RELAY DRIVER
A B
C B A
STTL TO TTL
RS
RC
PD
RD
SHD
Surge Protection
The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. The voltage withstand capability of pins `Tip', `Ring' and `RFs' is 450V with respect to ground, as shown in Table 1.
TABLE 1. PARAMETER TEST CONDITION PERFORMANCE (MAX) 450 (Plastic) 450 (Plastic) 450 (Plastic) 315 (Plastic) UNITS VPEAK VPEAK VPEAK VRMS
This device is intended for use with an appropriate secondary protection circuit scheme. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS , 15mARMS per leg, without any performance degradation.
Longitudinal Surge 10s Rise/ 1000s Fall Metallic Surge T/GND R/GND 50/60Hz Current T/GND R/GND 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall 11 Cycles Limited to 10ARMS
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HC5503PRC Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
HC5503PRC Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
2X 0.15 C A A 9 D1 D1/2 6 INDEX AREA N 1 2 3 E1/2 E1 9 2X 0.15 C B 2X 0.15 C A 4X C 0.08 C SEATING PLANE SIDE VIEW NX b 4X P D2 (DATUM B) 4X P 1 (DATUM A) 6 INDEX AREA NX L Ne 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 2 3 E2 7 E2/2 8 (Ne-1)Xe REF. D2 2N 5 0.10 M C A B 7 8 NX k A3 A1 0 TOP VIEW A2 A / / 0.10 C B E/2 E 2X 0.15 C B D
L32.7x7
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKC ISSUE C) MILLIMETERS SYMBOL MIN 0.80 0.23 TYP 0.90 0.20 REF 0.28 7.00 BSC 6.75 BSC 4.55 4.70 7.00 BSC 6.75 BSC 4.55 0.25 0.50 4.70 0.65 BSC 0.60 32 8 8 0.60 12 0.75 0.15 4.85 4.85 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 4 8/03 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P
D/2
9
9 CORNER OPTION 4X
C L
SECTION "C-C" C L
9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
10 L
L1 e CC
10
L L1 e
10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE
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